Publicaciones en las que colabora con Juan Manuel Barrientos Villar (4)

2009

  1. Reconfiguration-based time-to-digital converter for virtex FPGAs

    FPL 09: 19th International Conference on Field Programmable Logic and Applications

2005

  1. Boundary-scan interconnect test vector generation during VHDL synthesis

    EUROCON 2005 - The International Conference on Computer as a Tool

1996

  1. Integrated voltage regulator SPICE model

    Electronics Letters, Vol. 32, Núm. 12, pp. 1046-1047